Reduction of Drain Induced Barrier Lowering in DM‐HD‐NA GAAFET for RF Applications

In this research work, a dual‐metal hetero‐dielectric with nitride gate all around field effect transistor (DM‐HD‐NA GAAFET) has been proposed to address and mitigate an essential issue of drain induced barrier lowering and tunnelling leakage current. This device also provides better transconductance, output conductance, early voltage, and transforming growth factor so that it can also be used for radio‐frequency (RF) applications. In this structure, silicon dioxide (SiO 2 ) is used at the source side while the silicon nitride (Si 3 N 4 ) is used at drain side to reduce tunnelling of charge. In DM‐HD‐NA GAAFET, gate material engineering (GME) technique is also being used in which higher work function metal is used at source side in order to accelerate charge carriers while lower work function metal is used at drain side so that it can increase ON‐state current ( I ON ). The obtained results are compared with dual‐metal hetero‐dielectric with vacuum gate all around field effect transistor (DM‐HD‐VA GAAFET) to analyse its performance. In the proposed device structure, I ON increased by GME approach while I OFF decreased by hetero‐dielectric method so it improves I ON / I OFF ratio for DM‐HD‐NA GAAFET compared to DM‐HD‐VA GAAFET device.