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FLAXE, a SoC readout ASIC for electromagnetic calorimeter at LUXE experiment

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Abstract The design and qualification results of a System on Chip (SoC) Application-Specific Integrated Circuit (ASIC), called FLAXE, fabricated in 130 nm CMOS technology are presented. FLAXE is a readout ASIC designed for ECAL-p, a compact electromagnetic calorimeter being a part of a detector system for Laser Und XFEL Experiment (LUXE) proposed at DESY, Hamburg, as an extension to the European X-ray Free Electron Laser (XFEL) facility. ECAL-p is a sampling calorimeter with a very compact design targeting small Molière radius, comprising 16 (up to 20) layers composed of 3.5 mm (1 X0) thick tungsten absorber plates interspersed with silicon sensors. Sensor signal is read and shaped by the analogue readout channel, comprising a Charge Sensitive Amplifier (CSA) and a fully differential CR-RC shaper with 50 ns peaking time, which output is digitized in each channel by a 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). Data from ADC are collected into the ASIC internal memory and read out by the Data Acquisition (DAQ) system between Bunch Crossings (BXs). Around 1000 ASICs have been fabricated and a first batch of 142 ASICs has been packaged and tested. The results of the qualification procedure, as well as measurement result of a single ASIC are presented and discussed.
Title: FLAXE, a SoC readout ASIC for electromagnetic calorimeter at LUXE experiment
Description:
Abstract The design and qualification results of a System on Chip (SoC) Application-Specific Integrated Circuit (ASIC), called FLAXE, fabricated in 130 nm CMOS technology are presented.
FLAXE is a readout ASIC designed for ECAL-p, a compact electromagnetic calorimeter being a part of a detector system for Laser Und XFEL Experiment (LUXE) proposed at DESY, Hamburg, as an extension to the European X-ray Free Electron Laser (XFEL) facility.
ECAL-p is a sampling calorimeter with a very compact design targeting small Molière radius, comprising 16 (up to 20) layers composed of 3.
5 mm (1 X0) thick tungsten absorber plates interspersed with silicon sensors.
Sensor signal is read and shaped by the analogue readout channel, comprising a Charge Sensitive Amplifier (CSA) and a fully differential CR-RC shaper with 50 ns peaking time, which output is digitized in each channel by a 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC).
Data from ADC are collected into the ASIC internal memory and read out by the Data Acquisition (DAQ) system between Bunch Crossings (BXs).
Around 1000 ASICs have been fabricated and a first batch of 142 ASICs has been packaged and tested.
The results of the qualification procedure, as well as measurement result of a single ASIC are presented and discussed.

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