3D MIGCIM: A Material-Device-Circuit Co-Design for 3D Monolithic Integrated 4T2C ITO Gain Cell Compute-In-Memory on 2 nm GAA CMOS

The exponential growth in artificial neural networks demands energy-efficient, high-density accelerators. 3D monolithic integration achieves this by stacking memory directly over logic. Amorphous oxide channel transistors can enable a 3D monolithic technology with advanced Si CMOS. This work presents a 3D Monolithic Integrated 4T2C Gain-cell (MIG) embedded DRAM (eDRAM) based Compute-in-Memory (CIM) architecture for multiply-accumulate engines. We show that the Indium Tin Oxide (ITO) 4T2C eDRAM CIM array can be 3D monolithically integrated on 2 nm Si Gate All Around (GAA) CMOS technology node peripheral circuits for efficient area utilization, and higher compute density. A material-device-circuit co-design framework is demonstrated to optimize the devices based on material insights that meet circuit-level requirements. A novel cell layout is demonstrated for the ITO (L CH = 30 nm) 4T2C cell that overcomes the strong parasitic coupling disturbances occurring due to dense metal pitch. Based on this cell, a 64×128 eDRAM CIM macro for vector matrix multiplication between 62 8-bit binary inputs and 8-bit 62×15 ternary weights is shown. Furthermore, we also present a novel, area-efficient column ADC with single eDRAM CIM bitcell. Our 4T2C eDRAM CIM macro post-layout circuit simulations demonstrate 280.52 TOPS/W and 70.96 TOPS/mm 2. The 64X128 CIM macro occupies an area of 5945 µm 2 , with all the peripheral circuits under the array. The mixed signal CIM along with compact ADC approach and 3D monolithic integration with 2 nm Si peripheral circuits ensures > 7× TOPS/W and > 3.5× TOPS/mm 2 compared to 2D Si eDRAM CIM with similar architecture.