Proposal Topologies of RF Rectifiers Using 65nm TSMC MOS Technology

Radio-Frequency Energy Harvesting (RFEH) can be considered a promising solution for powering devices in the Internet of Things era, such as low-power wireless sensors, since RF electromagnetic waves are commonly found in diverse environments, due to different communication systems. To harvest the electromagnetic waves energy and convert them into Direct Current (DC), rectennas, which are composed of an antenna together with a rectifier, are used. However, the design of such rectifiers has two major challenges: the low spectral power density available and the dependence of circuit behavior on the operation temperature. To overcome the former, the Power Conversion Efficiency (PCE) of the circuit should be as high as possible, using, for instance, devices with low drop voltage. To improve the energy transfer from the antenna to the load, an Input Matching Network (IMN) is generally used. However, the rectifier input impedance varies with the temperature, which can degrade significantly the circuit performance. For this reason, to improve the circuit behavior, it would be desirable to have an RF design with low-temperature dependence. Schottky diodes are a common choice for RF rectifiers owing to their low conduction voltage and fast switching capability. Nevertheless, aiming to provide a better integration into commercial CMOS processes, such that the rectifier is placed together with the circuit it aims to power, it would be interesting to substitute Schottky with diode-connected MOSFETs. Therefore, this work aims to design rectifiers using a commercial RF 65nm CMOS process focusing on RFEH systems and considering the temperature influence. Two circuits were considered in this work: one basic Dickson charge pump, as presented in Fig. 1, and a 3-stage Dickson charge pump. In Fig. 1, VRF represents the RF source, M1 and M2 are the diode-connected transistors, CL is the load capacitance, and Cc is the coupling capacitance. In this circuit, the two diode-connected MOS operate alternately, one conducting at each half cycle of the input AC signal. Therefore, the voltage at CL is increased. For a 3-stage circuit, each basic cell of Fig. 1 is connected in cascade to the previous one. By using multiple stages, the output voltage can be further increased. However, there is a voltage drop at each device, in order to start its conduction, which can be a limiting factor for the circuit operation. For the determination of the devices width and length, an optimization tool incorporating the Imperialist Competitive Algorithm (ICA) has been used. The algorithm considers a Gaussian profile applied to the lower limit, center value, and upper limit fitness functions aiming to search for robust solutions regarding the variations of the manufacturing processes and environmental conditions. In the optimization process, the focus was a low temperature dependence while maximizing the output voltage. The TSMC RF CMOS 65nm PDK has been used, considering low threshold voltage transistors. The optimization was performed for the 3-stage circuit, whereas the one with just the first stage (parameters taken from the 3-stage optimization) was simulated for a comparison between their performances. A load of 1kW was considered, and the operation frequency was chosen as 2.45 GHz (ISM band). Fig. 2 presents the PCE as a function of the input power (Pin) for both circuits operating at different temperatures. It can be observed that the 1-stage circuit has provided a higher PCE than the 3-stage one. This can be understood by the fact that there are more transistors in the latter circuit and there is a voltage drop in each transistor, reducing the circuit efficiency. On the other side, the temperature has not affected the circuit behavior, which is significantly different from the rectifiers using Schottky diodes, in which the temperature increase results in a significant PCE reduction. In Fig. 3, the output DC voltage (Vout) obtained by these two circuits is presented as a function of the RF signal peak input voltage (Vin) at different temperatures. From this figure, it is clear that when increasing the number of stages, a higher output voltage can be obtained, making the 3-stage Dickson charge pump more adequate for supplying a low-power circuit. Nevertheless, a higher possible output voltage does not mean higher efficiency as previously demonstrated. In summary, in this work two MOS rectifiers, one with a single stage and a second one with 3 stages, were designed using commercial 65nm PDK aiming at RFEH applications operating at 2.45 GHz. The circuit has shown a low-temperature dependence. The higher the number of stages, the higher the output voltage. However, an efficiency reduction was observed for the multiple-stage rectifier. Figure 1