Memristor-Based Priority Encoder and Decoder Circuit

Introduction: Memristors, recognized as the fourth fundamental circuit element, exhibit unique features such as non-volatility, scalability, and energy efficiency. These characteristics make them ideal candidates for next-generation low-power digital systems. This study aims to design and analyze memristor-based 4:2 priority encoder and 2:4 decoder circuits to address the limitations of conventional CMOS designs in terms of power, speed, and area efficiency. Methods: The Voltage Threshold Adaptive Memristor (VTEAM) model was implemented in Verilog- A and simulated in Cadence Virtuoso to accurately capture the nonlinear switching characteristics of memristors. Hybrid CMOS–memristor logic gates (AND, OR, NAND, and NOR) were developed and used to construct the encoder and decoder circuits. The designs were validated through transient simulations, and their performance was compared with equivalent CMOS circuits based on parameters such as power consumption, propagation delay, and component count. results: The implementation phase of this work involves translating the proposed design methodology into a working simulation environment using Verilog-A with Cadence Virtuoso Spectre too. The process includes modeling, simulation setup, and integration of each component into the final priority encoder and decoder circuit. Verilog-A Memristor Model The memristor was implemented in Verilog-A using the VTEAM model framework, which defines the internal state variable dynamics based on applied voltage thresholds. The model incorporates both positive and negative threshold voltages, as well as mobility and fitting parameters that govern the device switching behavior. The analog block in Verilog-A handles the state update using differential equations that describe the rate of change of the internal state. Hard limits are applied to prevent the state variable from exceeding physical boundaries (typically between 0 and 1). The memristance is then computed based on this internal state. Figure 3 shows the symbol of memristor VTEAM model and Figure 4 shows the configuration for transient behaviour of memristor. The input sinusoidal signal having the amplitude of 1V and frequency of 100 KHz is applied to the circuit which is shown in Figure 4 for the validation of memristor model. Figure 3: Verilog-A Memristor VTEAM Model Symbol Figure 4: Circuit arrangement for validation of VTEAM memristor model Figure 5 and Figure 6 represents the transient behavior and PHL (pinched hysteresis curve) for the presented memristor model. Figure 6 represents the pinching of memristor at origin means zero input voltages approaches to zero input current. Figure 5: Transient analysis (input voltage and current waveform) for VTEAM memristor model Figure 6 I–V Characteristics of memristor showing pinched hysteresis loop Table 3 indicates the truth table of AND, OR, NAND and NOR gates and their respective resistance values corresponding to the output logic. These logic is verified using the cadence virtuoso spectre tool and the timing diagram for each gate is shown in Figure 7. In figure 7, it is observed that all gates logics are performed well with the memristor configuration. Table 3: Memristor based logic gates and corresponding Truth Table Type of Logical Gate Symbol with Internal Structure of MOS Based Logical Gates Truth Table AND IN_A IN_B OUT_Y 0 0 0 (MR = 1 KΩ) 0 1 0 (MR = 1 KΩ) 1 0 0 (MR = 1 KΩ) 1 1 1 (MR = 20 Ω) OR IN_A IN_B OUT_Y 0 0 0 (MR = 1 KΩ) 0 1 1 (MR = 20 Ω) 1 0 1 (MR = 20 Ω) 1 1 1 (MR = 20 Ω) NAND IN_A IN_B OUT_Y 0 0 1 (MR = 20 Ω) 0 1 1 (MR = 20 Ω) 1 0 1 (MR = 20 Ω) 1 1 0 (MR = 1 KΩ) NOR IN_A IN_B OUT_Y 0 0 1 (MR = 20 Ω) 0 1 0 (MR = 1 KΩ) 1 0 0 (MR = 1 KΩ) 1 1 0 (MR = 1 KΩ) Figure 7: Logic gates (AND, OR, NOT, NAND and NOR) verification timing diagram Now, Figure 8 shows the logic diagram of 4:2 priority encoder using the memristor logic gates (AND, OR, NOT, NAND and NOR). The logic diagram is implemented as per the truth table of priority encoder shown in Table 2. For the 4:2 priority enoder D0, D1, D2, and D3 are the inputs whereas, A, B and V are the ouputs. After the simplification using the K-map the logic equations are given below A= D_0+(D_1 ) ̅ D_2 (1) B=D_0+D_1 (2) V= D_0+D_1+D_2+D_3 (3) In the priority encoder D3 bit has highest priority and D0 bit has lowest priority. It means if D3 bit is ‘1’ and other bit are don’t care then the output must be ‘A=1, B=1, V=1’. Similarly if D3 bit is ‘0’ , D2 bit ‘1’ and other bits are don’t care then the output must be ‘A=1, B=0, V=1’, if ‘D1D2D3= 100’ then the output must be ‘A=0, B=1, V=1’ and if ‘D0D1D2D3= 1000’ then the output must be ‘A=0, B=0, V=1’. Here, V bit is indicating the valid input means if all input bits are ‘0000’ then it indicates the ‘0’ output approaches to invalid input. The all logics is verified using cadence virtuoso tool and shown in Figure 10 with the timing diagrams. Figure 8. Logic diagram for 4:2 memristor based priority encoder circuit Figure 9 Logic diagram for 2:4 memristor based decoder circuit. Similarly, figure 9 shows the logic diagram for memristor based 2:4 decoder circuit in which D0, D1, E are the inputs and O3, O2, O1, and O0 are the outputs. The logic equations for each output follows the binary number corresponding to its decimal input mapped with switch numbered ouput. The equations are as follows: O_3=(D_0 ) ̅.(D_1 ) ̅ (4) O_2= D_0 .(D_1 ) ̅ (5) O_1= D_1 .(D_0 ) ̅ (6) O_0= D_0 .D_1 (7) Figure 10 Output and Input waveforms for 4:2 priority encoder Figure 10 Output and Input waveforms for 2:4 decoder Results: Simulation results confirmed the correct logic functionality of the proposed circuits. The memristor-based 4:2 priority encoder exhibited a 49% reduction in power consumption and a 42% improvement in speed compared to its CMOS counterpart. Similarly, the 2:4 decoder demonstrated a 51% reduction in power consumption and 36% faster operation. Both designs also achieved higher area efficiency due to reduced transistor usage. The hysteresis and transient behaviors of the VTEAM model were validated, confirming its suitability for digital applications. Discussion: The study highlights the advantages of hybrid CMOS–memristor architectures in achieving low-power and high-speed digital logic. Despite the promising results, non-ideal factors such as device variability, stochastic switching, and endurance degradation remain key challenges for real-world implementation. The findings align with emerging research in memristor-based computing and suggest potential applications in edge computing, neuromorphic systems, and secure communication hardware. Conclusion: The successful design and simulation of memristor-based encoder and decoder circuits validate the feasibility and benefits of integrating memristors with CMOS technology. The observed improvements in power, speed, and area efficiency establish memristors as a strong alternative for next-generation low-power digital designs. Future work will focus on experimental validation and extending the proposed approach to more complex logic and memory architectures.