Javascript must be enabled to continue!
Design of XOR and XNOR Based Full Adder Circuits
View through CrossRef
This paper has a XOR / XNOR gate circuits produces separate and establishes a simultaneous XOR - XNOR function.. Due to stubby yield capacity and short-circuit energy dissipation, the power utilization and latency of these circuits is increasing A new one-bit adder hybrid circuit is chosen built on the effective gates of xor xnor or xor / xnor. Each prefer circuit has its own advantages as it is known for its high speed, low current drain, short delay product (PDP), galvanic ability, etc. Simulations of the planned models were carried out using Mentor Graphics to see the quality of these projects. The simulation results are based on the 130-nm CMOS engineering design. A recent technique of transistor sizing is implemented to improve the circuits ' PDP.
Blue Eyes Intelligence Engineering and Sciences Engineering and Sciences Publication - BEIESP
Title: Design of XOR and XNOR Based Full Adder Circuits
Description:
This paper has a XOR / XNOR gate circuits produces separate and establishes a simultaneous XOR - XNOR function.
Due to stubby yield capacity and short-circuit energy dissipation, the power utilization and latency of these circuits is increasing A new one-bit adder hybrid circuit is chosen built on the effective gates of xor xnor or xor / xnor.
Each prefer circuit has its own advantages as it is known for its high speed, low current drain, short delay product (PDP), galvanic ability, etc.
Simulations of the planned models were carried out using Mentor Graphics to see the quality of these projects.
The simulation results are based on the 130-nm CMOS engineering design.
A recent technique of transistor sizing is implemented to improve the circuits ' PDP.
Related Results
Four-bit Nanoadder Controlled by Five-Inputs Majority Elements
Four-bit Nanoadder Controlled by Five-Inputs Majority Elements
This paper presents a nano circuit of a full one-bit adder on the proposed five-input majority element. This innovative full adder design is used to development of a four-bit adder...
An Energy and Area Efficient Carry Select Adder with Dual Carry Adder Cell
An Energy and Area Efficient Carry Select Adder with Dual Carry Adder Cell
In this paper, an energy and area efficient carry select adder (CSLA) is proposed. To minimize the redundant logic operation of a regular CSLA, a dual carry adder cell is proposed....
Performance Comparison of Adder Topologies with Parallel Processing Adder Circuit
Performance Comparison of Adder Topologies with Parallel Processing Adder Circuit
In today’s modern era IC architecture design adders are become obligatory block. The growth in digitalization scenario to produce compact design products parameters like power, del...
Specific Design on Arithmetic Circuits with Low Power for VLSI Architectures
Specific Design on Arithmetic Circuits with Low Power for VLSI Architectures
The low power analog and digital systems are the major for any robotic applications. Designing low power and high-speed digital systems is one of the major and essential needs in V...
Verifying Deeds Simulator as a Savvy Tool for Half Adder and Full Adder Circuit Simulation
Verifying Deeds Simulator as a Savvy Tool for Half Adder and Full Adder Circuit Simulation
Accurate simulation of digital logic circuits is essential for ensuring their functionality before actual hardware implementation. The performance of the Digital Electronic Educati...
Energy efficient design and implementation of approximate adder for image processing applications
Energy efficient design and implementation of approximate adder for image processing applications
Approximate computing is a new technique that promises to speed up
computations while preserving a level of precision suitable for
error-tolerant systems such as neural netwo...
Booth Multiplier Based on Low Power High Speed Full Adder With Fin_FET Technology
Booth Multiplier Based on Low Power High Speed Full Adder With Fin_FET Technology
This paper proposes a novel Fin FET-based HSFA for the multiplier in order to overcome the issues of low speed operation. It is advantageous to use Fin FETs to construct the arithm...

