Low Temperature Bonding with Thin Wafers for 3D Integration

The ITRS roadmap for high-density TSV interconnects specifies maximum layer thicknesses of 5-15 µm in 2013 with a sub-micron layer-to-layer alignment accuracy. For 3D chip stacks with multiple layers it is not only necessary to handle and process such thin layers, but later on these thin layers have to be stacked and bonded. When it comes to wafer bonding for high-density TSV integration, most efforts have been given to developing Cu-Cu thermo-compression bonding and direct oxide bonding. Stacking of thin wafers can be performed either after the thin wafer is debonded or while the thin wafer is still bonded onto a carrier wafer. Bonding of the thin wafer while still mounted to the carrier wafer allows comfortable and safe wafer handling, but adds some complexity to the wafer bonding process.