Proposal of Pseudo Source and Drain MOSFETs for Evaluating 10-nm Gate MOSFETs

We propose a Pseudo source and drain metal oxide semiconductor field effect transistors (Ps-MOSFET) for investigating the electrical characteristics and physical phenomena in 10-nm gate MOSFETs. The Ps-MOSFET consists of a lower gate and an upper gate which electrically induce pseudo source and drain regions at the silicon surface. In this structure, the pseudo source/drain regions act as doped source/drain regions in a MOSFET. Since the pseudo source/drain regions are extremely shallow, short-channel effects are expected to be suppressed in this structure. To minimize the channel length and the leakage current, we optimized the substrate doping concentration to be approximately 1018 cm-3 by using a two-dimensional numerical simulation. In this case, we obtained a channel length of approximately 16 nm for 10-nm gate Ps-MOSFETs. Under this optimal doping condition, numerical calculations showed satisfactory transistor operations for the 10-nm gate Ps-MOSFETs: ON/OFF current ratio ∼106 and subthreshold slope ∼100 mV/decade. We also showed by calculation that the direct source-drain tunneling current was not negligible in the sub-10-nm regime.