DESIGN AND IMPLEMENTATION OF UART USING VERILOG: PARALLEL-IN-SERIAL-OUT AND SERIAL-IN-PARALLEL-OUT MODULES

The Universal Asynchronous Receiver-Transmitter (UART) is a key component in digital communication, enabling efficient serial data transmission with minimal hardware overhead. This paper presents the design and implementation of a UART module using Verilog Hardware Description Language (HDL). The focus is on two essential components: Parallel-In-Serial-Out (PISO) and Serial In Parallel Out (SIPO) modules, which facilitate data conversion for transmission and reception.The PISO module converts parallel data into a serialized format for transmission, while the SIPO module reconstructs serial data into parallel form upon reception. Both modules are designed with modularity and scalability in mind, ensuring efficient resource utilization and adherence to communication protocols. To ensure robust operation, the design incorporates start and stop bits, as well as clock synchronization to handle varying baud rates.The proposed design was verified through simulations under diverse conditions, demonstrating accurate functionality and reliability. Synthesis results confirmed compliance with timing constraints and efficient hardware resource usage, making the design suitable for FPGA implementation. The design was implemented and synthesis in QUARUS .This paper provides a comprehensive approach to UART design, offering insights into its practical applications in embedded systems and digital communication. The modular design ensures ease of integration into complex systems while maintaining high performance and reliability.