Search engine for discovering works of Art, research articles, and books related to Art and Culture
Javascript must be enabled to continue!
Performance Comparison of Adder Topologies with Parallel Processing Adder Circuit
View through CrossRef
In today’s modern era IC architecture design adders are become obligatory block. The growth in digitalization scenario to produce compact design products parameters like power, delay and area should be minimized. In most of the complex design of digital circuits, adder is an elementary factor. If the performance of digital adders is enriched, it would lead to quickening the binary operations in involved in the complex circuits. The constraints in the operation delay of an adder are due to carry propagation in the circuit. The adder topologies involved in this work includes Carry Save Adder, Carry Select Adder, Ripple Carry Adder and Kogge Stone Adder
IJAICT India Publications
Title: Performance Comparison of Adder Topologies with Parallel Processing Adder Circuit
Description:
In today’s modern era IC architecture design adders are become obligatory block.
The growth in digitalization scenario to produce compact design products parameters like power, delay and area should be minimized.
In most of the complex design of digital circuits, adder is an elementary factor.
If the performance of digital adders is enriched, it would lead to quickening the binary operations in involved in the complex circuits.
The constraints in the operation delay of an adder are due to carry propagation in the circuit.
The adder topologies involved in this work includes Carry Save Adder, Carry Select Adder, Ripple Carry Adder and Kogge Stone Adder.
Related Results
Four-bit Nanoadder Controlled by Five-Inputs Majority Elements
Four-bit Nanoadder Controlled by Five-Inputs Majority Elements
This paper presents a nano circuit of a full one-bit adder on the proposed five-input majority element. This innovative full adder design is used to development of a four-bit adder...
A framework for hierarchical compound topologies in species interaction networks
A framework for hierarchical compound topologies in species interaction networks
Hierarchical compound topologies of interaction networks that are segmented into internally nested modules have received scant attention, compared to simple nested and modular topo...
Booth Multiplier Based on Low Power High Speed Full Adder With Fin_FET Technology
Booth Multiplier Based on Low Power High Speed Full Adder With Fin_FET Technology
This paper proposes a novel Fin FET-based HSFA for the multiplier in order to overcome the issues of low speed operation. It is advantageous to use Fin FETs to construct the arithm...
Energy efficient design and implementation of approximate adder for image processing applications
Energy efficient design and implementation of approximate adder for image processing applications
Approximate computing is a new technique that promises to speed up
computations while preserving a level of precision suitable for
error-tolerant systems such as neural netwo...
Verifying Deeds Simulator as a Savvy Tool for Half Adder and Full Adder Circuit Simulation
Verifying Deeds Simulator as a Savvy Tool for Half Adder and Full Adder Circuit Simulation
Accurate simulation of digital logic circuits is essential for ensuring their functionality before actual hardware implementation. The performance of the Digital Electronic Educati...
An Energy and Area Efficient Carry Select Adder with Dual Carry Adder Cell
An Energy and Area Efficient Carry Select Adder with Dual Carry Adder Cell
In this paper, an energy and area efficient carry select adder (CSLA) is proposed. To minimize the redundant logic operation of a regular CSLA, a dual carry adder cell is proposed....
Simulation modeling study on short circuit ability of distribution transformer
Simulation modeling study on short circuit ability of distribution transformer
Abstract
Under short circuit condition, the oil immersed distribution transformer will endure combined electro-thermal stress, eventually lead to the mechanical dama...
Designing RNS-based FIR filter with Optimal area, Delay, and Power via the use of Swift Adders and Swift Multipliers
Designing RNS-based FIR filter with Optimal area, Delay, and Power via the use of Swift Adders and Swift Multipliers
Based on the Residue Number System (RNS), Finite Impulse Response filters have gained prominence in digital signal processing due to their efficiency in handling complex computatio...