Thinning of SOI Bonded Wafers by Applying Voltage during KOH Etching: Improvement of Thickness Variation by Reducing Leakage Current

A thinning technique for controlling thickness variation in Si-on-insulator (SOI) bonded wafers is presented. During KOH etching, voltage is applied between the supporting substrate and the etchant. The SOI thickness variation after the etch stop depends on the leakage current during etching. Reducing the current to the order of nanoamperes results in a thickness range of 50 nm. An average thickness of the superficial Si ranging from 0.3 to 2 µ m is obtained by etching 3±0.5-µ m-thick SOI bonded wafers, and depends on the applied voltage. Atomic force microscopy observation reveals a surface roughness of 1.4 nm (root-mean-square).