(Invited) Junctionless Device Cross-Section: A Key Aspect for Overcoming Boltzmann Tyranny

The demonstration of higher impact generate rate at relatively lower applied biases in a junctionless transistor (JLT) [1-2] has renewed interest in its device physics, operation and technology downscaling. This phenomenon is particularly interesting as it can lead to an associated steep current switching from off-to-on state with a subthreshold swing lower than 60 mV/decade [3-4]. A 3dimensional tri-gate JLT while offering immunity from short channel effects due increased gate controllability offers an additional degree of freedom apart from gate length and drain bias to tune the impact generation rate. Since JLT is a heavily doped device (figure 1(a)), the cross-section governs the concentration of carriers in the channel available for impact ionization and steep switching. Hence, the cross-section of a 3d JLT is expected to serve as a key facilitator for steep switching. Figure 1(b) shows the comparison of the 3d simulations exhibiting a sharp increase in current in a JLT with the available experimental data [1]. The default models of TCAD simulation tool [5] were calibrated to ensure a reasonable agreement with published results. Figure 1(c) shows the drain current (I ds) – gate voltage (V gs) characteristics of JLT for two different device cross-sections. The lower aspect ratio (AR = 0.2) JLT exhibits a lower subthreshold swing (SS) of 3 mV/decade while a JLT with AR of 1 showcases a conventional SS of 60 mV/decade. As shown in figure 1(d), results clearly indicate that device cross-section of a 3d JLT is crucial for overcoming the Boltzmann tyranny, and should be a crucial component for device design and operation. The research work demonstrates new possibilities through the optimization of 3d cross-section of a JLT for attaining a sharp enhancement of drain current at shorter gate lengths. References: [1] C.-W. Lee et al., Applied Physics Letters, 96, 102106, 2010. [2] S.M. Lee et al., IEEE Trans. Electron Devices, 60, 11, 3856-3861, 2013. [3] M. Gupta et al., IEEE Trans. Electron Devices, 65, 6, 2406-2412, 2018. [4] M. Gupta et al., IEEE Trans. Electron Devices, 64, 5, 2061-2066, 2017. [5] ATLAS User’s Manual, Silvaco. Figure 1