Low Power and Energy‐Efficient Design of MTJ / FinFET Circuits

ABSTRACT As technological nodes are scaled down to the nanoscale, power consumption emerges as a critical challenge in complementary metal‐oxide‐semiconductor (CMOS) technology. Emerging nanotechnologies and logic‐in‐memory (LIM) have been explored as promising solutions. The magnetic tunnel junction (MTJ), a spintronic device, consumes lower static power than the CMOS and FinFET technologies. Compared to the existing LIM‐based MTJ/CMOS designs, the proposed MTJ/FinFET systems consume less energy, have a shorter delay, and utilize less static power. These improvements are due to the FinFETs' improved gate control and its lowest 7 nm technology, and the precharge sense amplifier's (PCSA) charge sharing. A HSPICE circuit simulator simulates the design utilizing the 7 nm FinFET and perpendicular MTJ (PMTJ) models. According to the simulation results, the suggested MTJ/FinFET‐based OR/NOR, AND/NAND, and XOR/XNOR circuits perform noticeably better in energy consumption, delay, and power than LIM1 (a PCSA‐based design) and LIM2 (a modified PCSA‐based design). The results indicate that the proposed MTJ/FinFET designs improve overall efficiency compared with LIM2, which is the second‐best performing MTJ/CMOS in terms of static power and energy. The OR/NOR gates reduce static power, delay, and energy by 29.42%, 54.23%, and 68.42%; the AND/NAND design lowers them by 7.69%, 55.32%, and 58.18%; and the XOR/XNOR gates achieve reductions of 13.12%, 65.52%, and 70.27%, respectively. This study elucidates the superior performance of the MTJ/FinFET designs over existing LIM structures when logic circuits are implemented.