Design and Analysis of Low Power FINFET SRAM with Leakage Current Reduction Techniques

Abstract This article provides the development and examination of low-power FINFET SRAM with leakage current reduction techniques. The CMOS properties do not hold up well at lesser technology nodes due to scalability. Investigators are seeking alternatives to counteract the negative impacts of MOSFET scalability, and FINFET has been proven to be one of the ideal alternatives since it preserves less energy, removes short-channel effects, and minimizes leakage current. Since the number of portable gadgets that run on batteries has expanded dramatically, electronic items must be built to require minimal leakage power such that the gadget may run for extended periods of time. Initially, a 6t CMOS SRAM was designed and calculated for all the parameters. Later, DGFINFET SRAM was designed, and it can be observed that, compared with the CMOS-based design, the dynamic power dissipated by the FinFET-based 6T cell is reduced by 1.6 times, but it has equivalent static power dissipation. That is, the FinFET based 6T cell design significantly consumes less power than the conventional design. Also, it has 18% better hold SNM and 26% better RSNM, but its write SNM is 19% less than the CMOS 6T cell, showing that the FinFET based design has feeble writing ability. As a result, the FINFET SRAM was examined using various leakage current reduction strategies, resulting in a decrease in leakage current. Various leakage current minimization strategies are examined in order to minimize leaking current, and the suggested technique is shown to be the optimum for the development of low leakage current minimization that results in lower power leakage.