TCAD Calibration of High-Speed Si/SiGe HBTs in 55-nm BiCMOS

We present and discuss in this paper the challenges and solutions to calibrate the TCAD of high-speed DPSA-SEG Si/SiGe HBTs in 55-nm BiCMOS (B55) [1]. Both fabrication process and physical device calibration are addressed using the Sprocess and Sdevice modules of Synopsys®. A careful calibration of the fabrication process in 2D-TCAD is mandatory to simulate accurately the SiGe HBT performance. The first step is to reproduce precisely the device geometry captured with TEM pictures (see Fig. 1). Additional TEM analyses performed during the fabrication may also be required to fit perfectly the final transistor. Secondly, the vertical doping profile is calibrated both from SIMS (for As, Ge and B) and EDX (for As and Ge) measurements. EDX measurements in the transistor are increasingly important to capture the variation of the 1D doping profiles with the emitter width (cf. Fig. 2). In order to reproduce this effect, the injection of defects during the SiGe:C epitaxy has been implemented in TCAD simulation. In fact, the injection of interstitials and vacancies, which depends on the silicon area exposed during the growth, influences directly the Ge diffusion of the 2D doping profile. EDX measurements are also helpful to calibrate the lateral diffusions for the 2D doping profile. Even when these vertical profiles are well calibrated, the simulation of f MAX, R BX and C BC for DPSA-SEG architecture is still challenging due to the complexity of the base link formation, which includes the faceting at the edge of SiGe:C intrinsic base and the shallow trench isolation (STI), the boron diffusion through polycrystalline / monocrystalline interface, and hidden defects. Therefore the base link formation is simplified by skipping the faceting effect and the boron diffusion through the base link interface is analyzed through inspection of R BX, C BC and f MAX i.e. by a reverse engineering approach [2]. Resulting (f T, f MAX) performance presented in Fig. 3 match the measurements for the calibrated electrical model (see below). It will be shown in the extended paper that the impact of SiGe:C epitaxy growth temperature on the base thickness is well simulated. Considering now the electrical/physical device calibration, the following physical models are used in the B55 TCAD deck: - HD parameters [3] - Bandgap (BG) of SiGe structure and bandgap narrowing (BGN) [4] - Energy and relaxation time, mobility [5] - Intrinsic carrier densities, saturation velocity [6] - Default SRH, surface SRH and Auger models from Synopsys TCAD [7] - Default Lackner model for impact ionization from Synopsys TCAD [7]. The calibration of these models for each technology node is mandatory to match the electrical measurements. A sensitivity analysis approach has been used to adjust some model parameters in order to figure out which physical model has the largest impact on the different electrical performances. The resulting map of the impacts of the different physical models, which will be presented in the extended paper, provides precious information for TCAD calibration of current and future SiGe HBTs technology at STMicroelectronics. In conclusion, obtained 2D-TCAD electrical results fit well I B, I C, f T, f MAX and BV CEOmeasurements. The accuracy of TCAD simulation will be discussed in more detail in the extended paper.  References P. Chevalier et al, IEDM Tech. Dig., pp. 77-79, (2014) T. Rosenbaum, O.Saxod, V. T. Vu, D. Celi, P.Chevalier, M. Schröter and C. Maneux, Proc. IEEE BCTM, 64-67, (2015). G. Wedel and M. Schröter, Proc. IEEE BCTM, 237-244, (2010). D. B. M. Klaassen, J. W. Slotboom, H. C. De Graaff, Solid-state Electronics, 125-129 (1992) M. Michaillat, Ph.D thesis, Université Paris-Sud 11, (2010) G. Sasso, N. Rinaldi, G. Matz, C. Jungemann, Proc. IEEE SISPAD, 279-282, (2010) Sdevice documentation from Synopsis. Figure 1