Javascript must be enabled to continue!
Parallel-sequential adder-subtractor with the highest digits forward on neurons
View through CrossRef
The article deals with the development of a parallel-sequential adder-subtractor that performs arithmetic operations of addition and subtraction of binary numbers in the format with a fixed comma with the highest digits forward. The result of performing arithmetic operations is the sum and difference of binary numbers in the direct code of eight digits. The sum and difference of numbers is calculated on neuropositive elements, the transfer to the highest digits when summing and the loan from the highest digits when subtracting is determined by the majority elements. The algorithm for adding numbers in direct codes allows you to get the result in direct code. The signed digits of numbers determine which operation should be performed on numbers using the sum modulo two operation. If the characters are the same, the result will be zero. Otherwise, the result will be one. After that, the addition or subtraction operation is selected. Summation is performed if the numbers have the same signs, the result is assigned the sign of the first number. Subtraction is performed if the numbers have different signs, the result is assigned the sign of a larger modulo number. The adder-subtracter senior digits forward on neurons contains: block input, block comparatii, the block parallel-serial addersubtracter, the unit registers a larger number, the unit of determining the transfer and loan, a unit registers a smaller number of unit registers a result, the control unit, majority, threshold and neural elements. The device can be used as an arithmetic co-processor in a computer system. It significantly speeds up calculations of both simple arithmetic operations and results of various mathematical functions.
Title: Parallel-sequential adder-subtractor with the highest digits forward on neurons
Description:
The article deals with the development of a parallel-sequential adder-subtractor that performs arithmetic operations of addition and subtraction of binary numbers in the format with a fixed comma with the highest digits forward.
The result of performing arithmetic operations is the sum and difference of binary numbers in the direct code of eight digits.
The sum and difference of numbers is calculated on neuropositive elements, the transfer to the highest digits when summing and the loan from the highest digits when subtracting is determined by the majority elements.
The algorithm for adding numbers in direct codes allows you to get the result in direct code.
The signed digits of numbers determine which operation should be performed on numbers using the sum modulo two operation.
If the characters are the same, the result will be zero.
Otherwise, the result will be one.
After that, the addition or subtraction operation is selected.
Summation is performed if the numbers have the same signs, the result is assigned the sign of the first number.
Subtraction is performed if the numbers have different signs, the result is assigned the sign of a larger modulo number.
The adder-subtracter senior digits forward on neurons contains: block input, block comparatii, the block parallel-serial addersubtracter, the unit registers a larger number, the unit of determining the transfer and loan, a unit registers a smaller number of unit registers a result, the control unit, majority, threshold and neural elements.
The device can be used as an arithmetic co-processor in a computer system.
It significantly speeds up calculations of both simple arithmetic operations and results of various mathematical functions.
Related Results
Management of Vascular Defects in Digital Replantation
Management of Vascular Defects in Digital Replantation
207 cases of digital amputation (261 digits) with vascular defects were replantated during the past two decades. The vascular defect was managed with various methods. 240 digits (9...
Four-bit Nanoadder Controlled by Five-Inputs Majority Elements
Four-bit Nanoadder Controlled by Five-Inputs Majority Elements
This paper presents a nano circuit of a full one-bit adder on the proposed five-input majority element. This innovative full adder design is used to development of a four-bit adder...
Design of novel QCA-based half/full subtractors
Design of novel QCA-based half/full subtractors
Quantum-dot cellular automata (QCA) is an emerging nanotechnology and a possible alternative to the related issues of traditional complementary metal oxide semiconductors. It offer...
A 32-bit Ripple-Ling Hybrid Carry adder
A 32-bit Ripple-Ling Hybrid Carry adder
Abstract - This paper presents the design and implementation of a 32-bit Ripple Carry Hybrid Adder that combines the simplicity of the Ripple-Carry Adder (RCA) with the speed advan...
High-Speed Area-Efficient VLSI Architecture of Three Operand Binary Adder
High-Speed Area-Efficient VLSI Architecture of Three Operand Binary Adder
This paper proposes a novel high-speed three-operand binary adder architecture, namely the Han-Carlson adder, which mitigates the inherent limitations of traditional Carry Save Add...
HIGH-EFFICIENT VLSI ARCHITECTURE FOR THREE OPERAND BINARY ADDER
HIGH-EFFICIENT VLSI ARCHITECTURE FOR THREE OPERAND BINARY ADDER
This paper presents a VLSI architecture for a three-operand binary adder. The proposed design is based on a carry-select adder (CSLA) and Han-Carlson (HCA) adder. Carry-select adde...
Performance Comparison of Adder Topologies with Parallel Processing Adder Circuit
Performance Comparison of Adder Topologies with Parallel Processing Adder Circuit
In today’s modern era IC architecture design adders are become obligatory block. The growth in digitalization scenario to produce compact design products parameters like power, del...
Digital System Design
Digital System Design
The main objective of this chapter is to study and design various combinational circuits like Verification of Boolean Expression, Multiplexer, Demultiplexer Circuits, Code Converte...

