A 32-bit Ripple-Ling Hybrid Carry adder

Abstract - This paper presents the design and implementation of a 32-bit Ripple Carry Hybrid Adder that combines the simplicity of the Ripple-Carry Adder (RCA) with the speed advantages of Multiplexer (MUX)-based adders. In modern digital systems, high-speed arithmetic operations are essential, especially in processors, signal processing, and cryptographic applications, where delay, power consumption, and area are critical design parameters. The conventional RCA suffers from significant propagation delay due to the sequential carry propagation across each full adder stage, limiting its performance in high-speed applications. To address this limitation, the proposed hybrid architecture integrates a MUX-Based Adder (MBA) to reduce carry propagation delay and improve computational efficiency. The design achieves an effective trade-off between speed and hardware complexity by retaining the structural simplicity of RCA while enhancing performance through multiplexing techniques. The proposed adder is modeled using Verilog HDL. Performance evaluation is carried out based on key metrics such as delay, area utilization, and power consumption. Simulation and synthesis results demonstrate that the hybrid adder significantly reduces computation time compared to the conventional RCA, with optimized resource usage. The proposed design is therefore well-suited for high-speed and energy-efficient arithmetic units in modern digital processors and embedded systems. Keywords: Ripple-Carry Adder, MUX-Based Adder, Hybrid Adder, Digital Arithmetic, FPGA, High-Speed Computing