VECTOR-LOGICAL FAULT SIMULATION

Context. The main idea is the creation of vector-logical in-memory computing (VLC), which uses only read-write transactions on the address memory for faults-as-addresses simulation. There is no traditional logic. VLC is free from processor commands and ALU for computing organization and is therefore focused on implementation in SoC and FPGA. A vector-logical method of deductive matrix synthesis for the transportation of input faults, which has a quadratic computational complexity, is proposed. An inmemory simulator-automata for vector-deductive faults-as-addresses simulation, which based on read-write transactions for implementation in SoC is proposed. Objective. Development of a vector deductive method of fault simulation based on primitive read-write transactions for the analysis of logic circuits. Method. An input test set and a logical functionality vector are used. The proposed method is a development of the deductive vectors’ synthesis algorithm based on the truth table. The deductive matrix is intended for the synthesis and verification of tests using parallel simulation of faults-as-addresses combinations, based on read-write transactions over bits of deductive vectors in memory. Results. A vector method of the deductive matrices synthesis for the transportation of input faults vectors to the output of the element, was proposed. Data structures have been developed for parallel faults simulation of digital circuits based on a primitive readwrite transaction in matrix memory, where combinations of faults serve as address-columns. A sequencer of five blocks, that constitute a vector-logic computing, connected with deductive faults simulation based on read-write transactions, is proposed. Verification of models and methods on test examples has been performed. Conclusions. The scientific novelty consists in the development of the following innovative solutions: 1) a vector-logic method of synthesis of the deductive vectors matrix for parallel simulation of combinations of input faults-as-addresses, is proposed for the first time; 2) an automata for vector-deductive faults-as-addresses simulation, on the basis of read-write transactions, which is oriented for implementation in FPGA LUT, embedded online simulator SoC, as a core for faults simulation of RTL-level digital systems, was proposed for the first time; 3) the demonstration of the technological advantages of the vector-logic synthesis of deductive matrices is performed on numerous examples of traditional and RTL-logic, which accentuate the manufacturability of vectors in comparison with analytical deductive formulas during simulators construction; 4) a matrix of deductive vectors, as a set of vectorcolumns of Boolean derivatives is used to construct minimal tests for logical elements; 5) the recursive formula for the synthesis of the permutation of coordinates matrix in the logical activity vector makes it possible to significantly simplify the obtaining of the deductive matrix for faults-as-addresses simulation. The practical significance lies in the fact that the in-memory simulator will allow to obtain the speed of faults simulation of real digital blocks for SoC at the level of hundreds of nanoseconds. Complexity estimates of the corresponding algorithms are given.