Novel Hybrid SETMOS Logic for Ultra-low-power Applications

Abstract This paper investigates the Single-GateSingle Electron Transistors (SG-SETs) based hybrid SETMOS logic circuits for ultra-low-power applications at room temperature. The methodological design of the proposed hybrid SETMOS logic circuits is compatible with 22- nm CMOS bias and process. The widely acclaimed Mahapatra-IonescuBannerjee (MIB) model is modified to implement the proposed SG-SET and hybrid SETMOS logic circuits using Verilog-A. Logic inverter, two-input NAND, NOR, AND, OR, EX-OR, and EX-NOR logic gates are simulated at room temperature using novel SETMOS hybridization. The proposed work is compared with the 22-nm CMOS counterpart (simulated with the same setup). We found that the reduction in total power dissipation by 98.04%, 96.45%, 94.65%, 93.7%, 92.63%, 93.52%, 95.57% using hybrid SETMOS NAND, NOR, AND, EX-OR and EXOR gates than 22 nm CMOS logic gates. The proposed work is compared with other works of literature. We also examined the robustness of the proposed logic circuits against temperature variations from 77 K to 500 K.