An optimal design modeling of non-volatile dynamical reconfigurable FPGA using SOT-MRAM for ultra-low power applications

Abstract The rapid development of reconfigurable FPGA circuits will facilitate their use and operation at low cost. The design of internal memory of FPGA circuit controls their future development. Spin RAM and Magnetic RAM (MRAM) are the best solutions for FPGA for reducing power and writing time. In terms of memory technology, MRAM is becoming more and more attractive in the industry due to its promising capabilities. The physical design range still causes significant radiation effects such as write error rate, access time, tunnel breakage, and low MRAM power consumption. However, random MRAM writing processes affect their yield, so process variations should be investigated, which increases the complexity of yield analysis. For further enhancement of non-volatile FPGA circuits, we propose an optimal design modeling of non-volatile dynamical reconfigurable FPGA using SOT-MRAM for ultra-low power applications. We first introduce a spin-orbit torque-based MRAM (SOT-MRAM), which significantly reduces exposure to radiation caused by offline reading and writing. We design SOT-MRAM based on a double barrier magnetic tunnel connector (DMTJ) with two reference layers to ensure high power and right length. After that, we develop an optimal SOT-MRAM design using the butterfly induced sunflower optimization (BSFO) algorithm which optimizes the design parameters of writing processes. Finally, the simulation results of proposed design can be compared with the existing state-of-art designs in terms of different simulation metrics.