Reusable UVM Architectures for Mixed-Signal Designs

Contemporary mixed-signal System-on-Chip (SoC) solutions comprise more and more involved analog and digital modules. Although Universal Verification Methodology (UVM) testbenches have now become de facto industry standard for reusable digital verification IP (VIP), their reusability in mixed-signal environments is not yet fully explored. Conventional AMS verification flows are substantially dependent upon custom analog testbenches, in many instances leading to duplication of effort and atomistic approaches in work-flows within design teams. This paper presents a reusable UVM architecture that is organized into a structure to be used to a mixed-signal design. Incorporation of real-number modeling, uniform interface adapters and strong transaction-level stimulus extends a method between event-driven digital testbenches and continuous-time analog continuum. A case file is introduced on a reusable Analog-to-Digital Converter (ADC) verification IP, which manifestly exhibits gains in coverage, debug productivity and design cycle time. The methodology proposed is helpful to SoC teams so that aspects of faster closure with increased confidence can be made and at the same time provide standardization in reusable AMS VIP libraries that can be used in future designs.