3D Packaging Via Advanced-Chip-To-Wafer (AC2W) Bonding Enables Hybrid System-in-Package (SiP) Integration

ABSTRACT Increasing needs for high performance heterogeneous device applications leads to the implementation of new manufacturing and processing technologies. The realization of System-in-Package (SIP) applications via a vertical stacking approach is principally driven by various aspects. Main considerations for the realization are e.g. mixed signal/mixed technology integration, process optimization for each device and interconnect layer, enhanced communication bandwidth as well as decreased size and weight and subsequent stacking issues. Vertical stacking of chips using Advanced-Chip-to-Wafer bonding technology (AC2W) offers a new alternative to existing approaches like wafer-to-wafer 3D interconnect technology or chip-to-chip stacking technology. Furthermore AC2W combines highest flexibility for heterogeneous integration with high performance interconnect density and shortened time-to-market development needs. AC2W also accounts for the “Good Known Die” issue since only the “good” chips are attached to “good” dies on the wafer, therefore enabling highest manufacturing yield. AC2W allows stacking of chips with different physical dimensions from arbitrary technologies and substrates sizes as well as integration of multiple chips onto a single base chip of the substrate wafer. The presentation will focus on a manufacturing platform suitable for AC2W on R&D level as well as for volume production, including a description of the process flow while maintaining different interconnect types. Further properties of the technology, including newly developed Flip-Chip and Chip-to-Wafer bonder systems, will be described. Achievements for a specific 3D interconnect type, where face-to-face orientation of the chips is realized, are given as an example. Finally we will discuss possibilities on the integration of mixed technologies such as MEMS, integrated passives or optical components with the AC2W technology.