Autonomous UART recovery: integrating Hamming ECC with ML-driven fault diagnosis and shadow channel failover

Abstract The fault-tolerant UART architecture described in this paper combines Hamming(12, 8) error correction, a machine-learning fault classifier implemented in hardware, autonomous fault recovery, and a shadow channel mechanism, validated through fault injection on an field-programmable gate array (FPGA). A protocol-aware dataset of 50 000 balanced frames with six fault classes (parity, framing, overrun, break, bit corruption, and normal) was used to train a decision-tree classifier, pruned to 15 nodes and represented using 128 LUT6 primitives with a 12-cycle combinational inference path. The Hamming(12,8) codec processes a 12-bit codeword in a parallel shadow channel while maintaining standard 8N1 framing on the primary channel, ensuring full backward compatibility. The escalation threshold F 5 ⩾ 2 is directly proportional to the minimum Hamming distance of 4. Five independent fault injection runs with different random seeds demonstrate statistical robustness. The design, implemented on a DE10-Standard board with a Cyclone V FPGA at 115 200 baud and 16× oversampling, achieves 99.76 % ± 0.03 % classification accuracy, an end-to-end failover latency of 3.2  µ s, and sustained-fault throughput degradation of less than 0.37%. The architecture reduces previously undetected errors by up to 98.5% compared to a conventional UART baseline, provides 4.2× multi-fault coverage over Hamming-only designs, and incurs 13.4% adaptive logic module and 12% power overhead, with no communication loss observed under all evaluated fault scenarios.