Hybrid Bonding for 3D Integration

ABSTRACT With end applications in the high performance server, mobile computing and smart phone space demanding ever higher performance of microelectronic devices while reducing power consumption and package size, the industry is preparing for the market introduction of 3D stacked devices based on TSV technology. Recently, it has been reported that, in general the technological challenges related to the manufacture of 3D integrated devices have been solved. This is evident by first product announcements that will leverage 3D IC technology in high end mainstream electronics products. It is reported that Intel will be using 3D stacked memory in its Knights Landing processor products. [1] Furthermore, NVIDIA has announced to be using SK Hynix’ HBM (High Bandwith Memory) in it's Volta family of graphics processing products. [1, 2] From a technological perspective, the use of 3D technology is a natural choice, as it provides for x increase in bandwith, y decrease in power consumption and zabc as presented by Samsung for the case of 3D stacked memory. The remaining challenge that is reported to slow down a more widespread adoption of 3D TSV technology is cost. [1] Besides the benefits reported for 3D stacked memory, 3D integration technology is gaining traction from yet another angle. The semiconductor industry is facing exponentially increasing difficulties related to further extending Moore s law, which translates to steeply increasing costs on one-hand-side and technological hurdles, which may put a hard stop to further shrinking transistor size on the other side. One major alternative for the extension of Moore s law is the use of monolithic 3D integration, which relies on stacking two active layers of transistors onto one another, coupled together with extremely high density through silicon connections. Some studies predict that monolithic 3D integration will be more cost effective than further scaling devices size in x/y direction in the 2D regime. This is mainly due to the fact that smart partitioning may also help to reduce cost for the manufacture of the individual layers by leveraging a more streamlined process with fewer processing steps that may yet be more optimized with respect to providing higher device performance in the individual layers, as partitioning would allow for applying process conditions to one layer that might not be compatible to the other layer. One key technology enabling such monolithic 3D integration is wafer bonding technology that enables wafer level bonding with an ultra-high alignment precision. While this technology is mandatory for the realization of monolithic 3D integrated devices, it also offers great promise for cost reduction of 3D stacked memory devices as well, potentially enabling wide-spread adoption of 3D integrated memory devices in a broad range of applications. The first part of this paper reviews alignment accuracy considerations for different applications and application scenarios as well as introducing face-to-face alignment and hybrid bonding technology. Next, the paper reviews the process flow for hybrid bonding and introduces EV Group’s latest generation technology for ultra-high precision aligned wafer level bonding based on the patented SmartView® face-to-face alignment principle. Finally, the paper concludes with presenting alignment accuracy data achieved with this technology.