CMOS BASED ARCHITECTURE FOR HIGH SPEED BCD ADDITION

Accurate decimal calculations are a fundamental requirement in accurate-operated domains such as finance and scientific research. Traditional binary arithmetic circuits, although widely used, often introduce rounding inaccuracy that can cascade in adequate errors in sensitive applications. To address this challenge, this research examines solution by designing the decimal arithmetic circuit using the CMOS-based binary-coded decimal (BCD) Adders. Unlike software-level reforms, the proposed approach embedded accuracy in circuit design itself. Decimal Adders are modeling and valid through the rhythm using 90nm CMOS technology, which ensures high loyalty in logic implementation. In addition, both Cadence virtuoso and tanner are organized to evaluate demonstration matrix using wide simulation, power efficiency and operating delays using EDA equipment. The benchmark comparison with existing architecture reveals significant reforms, especially in power consumption. This study confirms the argument that integrating the decimal arithmetic directly into silicon can greatly increase both reliability and computational accuracy in important systems.