Performance Comparison of 8-Digit BCD Adders using CLA and Brent–Kung Architectures

Abstract - Binary Coded Decimal (BCD) adders play a crucial role in digital systems requiring precise decimal arithmetic, particularly in financial computing, commercial applications, and modern processors. The efficiency of a BCD adder is strongly influenced by the underlying binary adder architecture used for carry generation and sum computation. In this work, an 8-digit BCD adder is designed and implemented using two different architectures: the Carry Look-Ahead Adder (CLA) and the Brent–Kung Adder (BKA). Both designs are modeled in Verilog Hardware Description Language (HDL) and verified through simulation. The performance of the two architectures is evaluated in terms of speed and power consumption. Synthesis results reveal that the Brent–Kung based BCD adder achieves a propagation delay of 2.43 ns, outperforming the CLA-based design which exhibits a delay of 3.58 ns. Furthermore, the Brent–Kung architecture demonstrates superior power efficiency, consuming 25.083 mW compared to 27.020 mW for the CLA implementation. These findings highlight that the Brent–Kung Adder provides significant improvements in both speed and energy efficiency for multi-digit BCD addition. Consequently, the Brent–Kung based BCD  adder  is  more  suitable  for  high- performance decimal arithmetic applications in modern digital and VLSI systems. Key Words : BCD addition,CLA,BKA and Verilog HDL