Search engine for discovering works of Art, research articles, and books related to Art and Culture
Javascript must be enabled to continue!
Characteristics and Applications of CAAC-IGZO FET with Gate Length of 13nm
View through CrossRef
A field-effect transistor (FET) with a gate length of 13 nm having a c-axis aligned crystalline In-Ga-Zn oxide (CAAC-IGZO) channel was fabricated. The CAAC-IGZO FET has an off-state leakage current of 200 yA/μm, a cutoff frequency of 60GHz, and a maximum oscillation frequency of 16GHz. A CAAC-IGZO FET, though it is a small transistor, withstands voltages up to approximately 2.5 V. It also has stable current characteristics with less temperature dependence than Si devices. We have constructed an equivalent-circuit model of the CAAC-IGZO FET and designed an RF amplifier to show CAAC-IGZO FET's applicability to the GHz-range RF circuitry.
Title: Characteristics and Applications of CAAC-IGZO FET with Gate Length of 13nm
Description:
A field-effect transistor (FET) with a gate length of 13 nm having a c-axis aligned crystalline In-Ga-Zn oxide (CAAC-IGZO) channel was fabricated.
The CAAC-IGZO FET has an off-state leakage current of 200 yA/μm, a cutoff frequency of 60GHz, and a maximum oscillation frequency of 16GHz.
A CAAC-IGZO FET, though it is a small transistor, withstands voltages up to approximately 2.
5 V.
It also has stable current characteristics with less temperature dependence than Si devices.
We have constructed an equivalent-circuit model of the CAAC-IGZO FET and designed an RF amplifier to show CAAC-IGZO FET's applicability to the GHz-range RF circuitry.
Related Results
Characteristics and Applications of CAAC-IGZO FET with Gate Length of 13nm
Characteristics and Applications of CAAC-IGZO FET with Gate Length of 13nm
A field-effect transistor (FET) using CAAC-IGZO, a crystalline oxide semiconductor having a c-axis alignment, is considered for application to various circuits. In particular, its ...
P-410 A modified artificial cycle-frozen embryo transfer(mAC-FET) protocol with evidence of corpus luteum(CL) formation as determined by serum relaxin-2 in early pregnancy :a prospective proof-of-concept study
P-410 A modified artificial cycle-frozen embryo transfer(mAC-FET) protocol with evidence of corpus luteum(CL) formation as determined by serum relaxin-2 in early pregnancy :a prospective proof-of-concept study
Abstract
Study question
Can a mAC-FET protocol for endometrial preparation in ovulatory patients lead to formation of a CL as ev...
Floating gate effect in amorphous InGaZnO thin-film transistor
Floating gate effect in amorphous InGaZnO thin-film transistor
In recent years, considerable attention has been paid to amorphous indium gallium-zinc-oxide (a-IGZO) thin film transistors (TFTs) for high performance flat panel display, such as ...
Notched Gate and Graded Gate Oxide Processing for Reduced Capacitance Application in RF MOSFETs
Notched Gate and Graded Gate Oxide Processing for Reduced Capacitance Application in RF MOSFETs
As the demands of RF applications are rising, optimization of internal MOSFETs capacitances is a key issue to improve the cut-off frequency. In this abstract we report the developm...
P-551 Association between the length of in vitro culture and mode of ART and the initial se-hCG rise in ongoing singleton pregnancy
P-551 Association between the length of in vitro culture and mode of ART and the initial se-hCG rise in ongoing singleton pregnancy
Abstract
Study question
Does the length in vitro and mode of ART (fresh and frozen cycles) impact the se-hCG rise in cycles with...
Glioma Biopsy Based on Hybrid Dual Time-Point FET-PET/MRI—A Proof of Concept Study
Glioma Biopsy Based on Hybrid Dual Time-Point FET-PET/MRI—A Proof of Concept Study
Neuroimaging based on O-[2-(18F)fluoroethyl]-l-tyrosine (FET)-PET provides additional information on tumor grade and extent compared with MRI. Dynamic PET for biopsy target selecti...
Investigation of the Gate Degradation Induced by Forward Gate Voltage Stress in p-GaN Gate High Electron Mobility Transistors
Investigation of the Gate Degradation Induced by Forward Gate Voltage Stress in p-GaN Gate High Electron Mobility Transistors
In this work, we investigated the degradation of the p-GaN gate stack induced by the forward gate voltage stress in normally off AlGaN/GaN high electron mobility transistors (HEMTs...
Effect of Gate-Electrode/Gate-Dielectric Interlayer on Gate Screening of Remote Phonon Scattering in InGaZnO Thin-Film Transistor with High-k Gate Dielectric
Effect of Gate-Electrode/Gate-Dielectric Interlayer on Gate Screening of Remote Phonon Scattering in InGaZnO Thin-Film Transistor with High-k Gate Dielectric
InGaZnO thin-film transistors with various SiO2 thicknesses (0, 3.5, 8.5, 18.8 nm) in double-layered gate dielectric (NdHfO/SiO2) and different gate doping concentrations (2.4×1015...