High-Performance 4-Wide Superscalar Out-of-Order RISC-V Processor

The continuous demand for high computational throughput in modern processors has encouraged the development of architectures capable of issuing and executing multiple instructions per clock cycle. This paper presents the design and implementation of a 4-wide superscalar out-of-order RISC-V processor that exploits instruction-level parallelism through dynamic scheduling, register renaming, and speculative execution. The proposed design incorporates a Reorder Buffer (ROB), Issue Queue (IQ), and Load-Store Queue (LSQ) to manage instruction dependencies and ensure precise exception handling. A hybrid branch prediction unit with a Branch Target Buffer (BTB) and Return Address Stack (RAS) is employed to minimize control hazards and improve pipeline utilization. The processor is evaluated using standard RISC-V benchmarks to analyze parameters such as Instructions Per Cycle (IPC), execution latency, and branch prediction accuracy. Experimental results demonstrate a significant improvement in performance compared to a single-issue inorder baseline, achieving higher IPC while maintaining correctness and hardware efficiency. The presented design highlights a balanced trade-off between performance gain and hardware complexity, making it a promising model for future high-performance RISC-V cores.