Implementation of High Performance 6T-SRAM Cell

Abstract Now a days each and every device equipped with large capacity memories in order to full fill all the needs of customers. And there are some other parameters which plays an important role in the determination of performance of the device they are power consumption and delay. In many widgets, memory is an integral part and its size also scales down as the device size is reduced. For this reason, every computerized device has low power and high speed is a prime concern. Current day scenario suggests that 6T SRAM is commonly used for the SRAM based memorydesignsas they are advantageouscompared to other cells. Low power is the major concern of today’s electronics industries where, Static as well as Dynamic power dissipation are the two key parameters that should be taken into consideration. To meet consumer needs high bandwidth and low power and high speed consuming storages are also required. This paper mainly focuses on reducing powerdissipation of Static Random Access Memory (SRAM). Power reduction and Delay reductions are the major challenge of digital Industry. A simple and advantageous configuration of a SRAM cell is by connecting two CMOS inverters back to back. This configuration has good noise immunity.