Low-power Multi-bit Delta-Sigma Modulator based on Passive and Attenuationless Summation Scheme

In the field of delta-sigma modulators, reducing system power consumption without sacrificing accuracy has become a challenge. The summing circuit, as the main part of the cascade-of-integrator-in-feedforward delta-sigma modulator, consumes a significant amount of power in active summing. On the other hand, passive summing circuits have low power consumption but can cause attenuation in the summing results. This article proposes a low-power multi-bit delta-sigma modulator based on passive and attenuationless summation scheme. The summation circuit achieves multiplication of the voltage signal carried on the summation capacitor through bidirectional sampling technique, compensating for the inherent attenuation caused by passive summation, thus eliminating the need for active OTA to achieve perfect summation. A 2-order delta-sigma modulator based on 4-bit 1-order passive noise-shaping (NS) SAR quantizer is designed to verify the scheme. By combining a passive NS SAR as the 4-bit quantizer and the third-stage integrator of the system, and incorporating an energy-efficient cascode floating inverter amplifier (FIA) structure as the core active OTA, these elements have significantly enhanced the energy-efficiency of the modulator. Simulation results show that at a supply voltage of 1.2 V and a bandwidth of 20 kHz, the SNDR reaches 102.62 dB, power consumption is only 148.32 μW, and Schreier figure-of-merit (FoM) of SNDR is 183.92 dB.