Low-power Multi-bit Delta-Sigma Modulator based on Passive and Attenuationless Summation Scheme

In the field of delta-sigma modulators, reducing system power consumption without sacrificing accuracy has become a challenge. The summing circuit, as the main part of the delta-sigma modulator, consumes a significant amount of power in active summing, although it can achieve perfect summation. On the other hand, passive summing circuits have low power consumption but can cause attenuation in the summing results. The objective of this article is to explore how to achieve perfect summation in a passive manner. This article proposes a low-power multi-bit delta-sigma modulator based on passive and attenuationless summation scheme. The summation circuit achieves multiplication of the voltage signal carried on the summation capacitor through bidirectional sampling technique, compensating for the inherent attenuation caused by passive summation, thus eliminating the need for active OTA to achieve perfect summation. A pseudo 3-order delta-sigma modulator based on 4-bit quantizer is designed to verify the scheme. Simulation results show that at a supply voltage of 1.2V and a bandwidth of 20kHz, the SNDR reaches 102.62dB, power consumption is only 148.32μW, and Schreier FoM of SNDR is 183.92dB.