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Switched‐capacitor‐based boost multilevel inverter topology with higher voltage gain

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This study proposes a new switched‐capacitor‐based multilevel inverter topology with a single dc voltage source. The proposed topology finds its suitability for renewable energy applications with low voltage. Seven‐level (7L) output voltage is achieved across the load with triple‐voltage gain employing 2 capacitors and 12 switches. Self‐voltage balancing of capacitor voltages, parallel operation of capacitors during discharging mode, reduced voltage stress, and bipolar output voltage generation without using backend H‐bridge are the major features of the proposed topology. Furthermore, a generalised structure of the proposed topology has also been discussed here. A comparison with other similar topologies with single‐source 7L configuration has been carried out to show the advantages of the proposed topology with reduced switch count. Experimental results have been provided to verify the performance of the proposed topology with different operating conditions.
Title: Switched‐capacitor‐based boost multilevel inverter topology with higher voltage gain
Description:
This study proposes a new switched‐capacitor‐based multilevel inverter topology with a single dc voltage source.
The proposed topology finds its suitability for renewable energy applications with low voltage.
Seven‐level (7L) output voltage is achieved across the load with triple‐voltage gain employing 2 capacitors and 12 switches.
Self‐voltage balancing of capacitor voltages, parallel operation of capacitors during discharging mode, reduced voltage stress, and bipolar output voltage generation without using backend H‐bridge are the major features of the proposed topology.
Furthermore, a generalised structure of the proposed topology has also been discussed here.
A comparison with other similar topologies with single‐source 7L configuration has been carried out to show the advantages of the proposed topology with reduced switch count.
Experimental results have been provided to verify the performance of the proposed topology with different operating conditions.

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