Low-Temperature Ozone Atomic-Level Trimming on Ge Interfused Channel with Subthreshold Characterization Enhancement for Gate-All-Around Si Nsstransistors

Recently, stacked nanowire/nanosheet GAAFETs have been under intensive investigation owing to their excellent electrostatics and short-channel control, which can fulfill the requirement of the 5-nm technology node and beyond. However，GAAFETs are affected by the overall thermal budget of the integration process, and after channel release removes the SiGe stack, the presence of Ge residues on the Si channel surface increases the interfacial trap charge, leading to increased defects on the channel surface, which affects the subthreshold characteristics of the device and increases the SS. Due to the tendency to overcorrode during the channel release process and the effect of Ge diffusion, the NS surface roughness becomes larger, leading to enhanced surface scattering and resulting in a decrease in the effective mobility of the carriers, in which the surface roughness change mainly affects the surface roughness scattering and Coulomb scattering of the carriers. Conventional interface treatment methods cannot accomplish the reduction of SS and surface roughness at the same time, so in this paper, we propose a low-temperature ozone atomic-level stripping process method to thin the trench of the gate-all-around NS device. Removing Ge diffused into the trench due to the thermal budget, reducing the trench surface roughness and the surface state, and repairing the free Si and Ge bonds caused by the high thermal budget and the diffusion of Ge. Finally, the device subthreshold characteristics are optimized. In this paper, the verification is first carried out on capacitor wafers by using low temperature ozone atomic level stripping treatment on silicon wafers with simulated channel surfaces for 1/2/5 times, respectively. After O3 treatment, the interface state density is significantly reduced, the interface optimization results results are shown in Fig1. At the same time the above operation makes the thickness of the oxide layer reduce significantly, the EOT is reduced, resulting in a lower K value. So two O3 treatments are applied to the channel surface after channel release in the actual device. The result SS is reduced from 67.5 to 64.3 mV/dec for PFET and reduced from 67.8 to 64.8 mV/dec for NFET (Fig. 2), the device characteristics are significantly improved. N-type MOSCAPs were fabricated with the standard high-k/metal-gate (HK/MG) on a Si0.7Ge0.3 epitaxy layer on p-type bulk-Si (100) wafers. The process flows and key process-step techniques are shown. To reflect the channel interface issues of GAA NSFETs, the capacitors were fabricated on the epitaxy substrate with at a rapid thermal annealing (RTA) and a simulated channel release process. Firstly, 12 nm Si and 18 nm Si0.7Ge0.3 were epitaxially grown on the substrate as the channel surface, and an RTA of 850 ℃ for 75s was performed based on the general thermal budget requirement of the front-end process. Next, the SiGe layer was removed by channel release solution. Afterwards, the substrate was processed by O3 for 2 second after wet-etch SiGe 20s, and then rinsed in DHF for 20s to remove the oxidation. Figure 1