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Design of 9:2 compressor using FinFET
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Abstract
Multiplier is an essential component that is used commonly in any digital circuits. In general, for any digital circuits, multipliers occupy larger area; have long latency and their power consumption is more. Thereby, enhancing the performance of multipliers is quite important. Compressors are used to reduce the partial products so that the improved performance of multipliers can be achieved. In this paper, a new structure of 9:2 compressor is proposed in which the circuit is implemented with different combinations of 3:2, 4:2, 5:2 and 6:2 compressors. In this work, instead of bulk CMOS technology, circuits are implemented using FINFETs as they provide better gate control property, lower short channel effects. All the compressor circuits have been implemented using Cadence Virtuoso Simulator with FINFET 32nm technology. All the circuits are implemented to analyze the performance in terms of power, delay and transistor count.
Title: Design of 9:2 compressor using FinFET
Description:
Abstract
Multiplier is an essential component that is used commonly in any digital circuits.
In general, for any digital circuits, multipliers occupy larger area; have long latency and their power consumption is more.
Thereby, enhancing the performance of multipliers is quite important.
Compressors are used to reduce the partial products so that the improved performance of multipliers can be achieved.
In this paper, a new structure of 9:2 compressor is proposed in which the circuit is implemented with different combinations of 3:2, 4:2, 5:2 and 6:2 compressors.
In this work, instead of bulk CMOS technology, circuits are implemented using FINFETs as they provide better gate control property, lower short channel effects.
All the compressor circuits have been implemented using Cadence Virtuoso Simulator with FINFET 32nm technology.
All the circuits are implemented to analyze the performance in terms of power, delay and transistor count.
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