Collective D2W Hybrid Bonding for 3D SIC and Heterogeneous Integration

Heterogeneous integration describes the coalescence of multiple developments of the past years. On the one hand, 3D integration technologies have been emerged and are widely available in high volume manufacturing environment. On the other hand, several advanced packaging technologies, such as fan out wafer level packaging or interposers are high volume technologies. Depending on the device architecture and level of integration, several integration methods at different manufacturing levels can be used to create heterogeneous integrated systems. Here we will focus mainly on the 3D stacked IC (3D SIC), bridging the gap between pure backend integration flows such as Fan Out Wafer Level Packaging, and between wafer to wafer integration schemes as done in system on chip integration. Wafer bonding and especially fusion and hybrid wafer bonding are readily available in mass production at major foundries, integrated device manufacturers. While the driving forces for the technology are 3D integration processes for memory, image sensors, this will not be feasible for heterogeneous integration. The major benefit for heterogeneous integration is coming at the system level. However, this means that different silicon nodes, compound semiconductors for photonic, power devices or RF filters coming from different fabs on difference wafer sizes need to find their way on a silicon base substrate. As fusion and hybrid bonding are compatible with front end manufacturing, all sequential die to wafer (D2W) approaches are not. Mainly particle generation and in many cases several hours of placement time, make particle sensitive processes such as fusion bonding very difficult to be integrated for D2W processing. While particle requirements of ISO1 can be mastered inside the equipment, still the population time and moving bond heads over the wafer will influence yields considerably. However, D2W equipment will be detrimental for heterogeneous integration. Combining segmented dies in an advanced package can be done by two different bonding technologies, namely sequential die bonding or a collective die bonding approach. For the collective bonding, individual dies are populated and tacked either on an interposer or a so-called handling carrier, depending on the bonding technology applied. In case of tacking die face-down on an interposer or other active silicon die, bonding is usually being done by thermal bonding. Here, heating and cooling of the substrates are only done once, considerably reducing process cost and thermal budget of the underlying substrate. The second case is tacking the dies face up on a carrier substrate. This reconstructed dies on a carrier can now be processes again on wafer scale, this means preprocessing steps such as direct bonding can be done before bonding the wafers using fusion or hybrid bonding. In this presentation we will show different integration approaches for collective die bonding for fusion as well as hybrid bonding. For both processes, results in terms of die placement and sequential alignment accuracy of the integrated process will be compared and discussed, together with current and potential applications of these processes for future devices.