Design of ripple carry adder using pseudo-NMOS, dynamic circuits and pass transistor logic

The present work is mainly focused on area and power of ripple carry adder by using different types of circuit families like pseudo-NMOS logic, dynamic circuit logic and pass transistor logic are used. The main objective of this paper is to reduce the pull-up network or PMOS transistor counts. Because the flow of mobility of electron in PMOS is low so it takes more time. To reduce the PMOS counts, power consumption for RCA by using this logic. In pseudo-NMOS logic, instead of using every PMOS use only one PMOS that is connected to ground. In dynamic circuit logic, instead of connecting PMOS to ground to give clock signal to PMOS to reduce the static power dissipation. In pass transistor logic it uses only pull-down network that means NMOS logic so half of the transistor gets reduced. Based on these results we know that, which logic is efficient to construct the Ripple Carry Adder by using Tanner tool version 13.