Method of frequency-phase detection used in ADC based on PLL circuit

The phase‑locked loop (PLL) is an integral part of many electronic products in modern electronics and radio engineering, which is used to form and process analog and digital signals. One of the non‑standard applications of the PLL circuit is to implement an analog voltage‑to‑pulse converter. This application of the PLL circuit allows you to create an analog‑to‑digital converter (ADC) with high resolution, and the implementation features of the PLL circuit can provide a number of advantages, such as high noise immunity, compensation for the errors of passive elements, operation in a wide temperature range, etc. The accuracy of the conversion in such a device depends on both the separately designed blocks of the PLL circuit and the parameters of the system as a whole. The paper discusses the implementation of a digital frequency‑phase detector (FFD) operating in the range from 0 to 2p. The basis of his work is the method of frequency‑phase detection, which reduces the time of transients in the PLL circuit, and also eliminates the detection of coherent and multiple frequencies of the reference signal.