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Substrate Warpage Study for Heterogeneous Packages
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Warpage formation in semiconductor packages is generally known to occur from coefficient of thermal expansion (CTE) mismatches between multilayered materials with different properties. The different properties of each printed circuit board (PCB) layer will yield different expansion rates, which will lead to significant high warpage formation under the reflow temperature. The presence of significant warpage will further induce opened solder joint risks, solder joint collapse for flip chip ball grid arrays (FCBGAs) and so on. Package warpage is an important factor that impacts board assembly yield, delamination, solder joint fatigue reliability, and other thermal stress issues. Reducing warpage is a primary concern when trying to enhance the service life of a package. For years the IC industry has been driven by Moore’s Law assumption that the functionality that fits on a single die will double every 18 to 24 months. As minimum dimensions have shrunk from 14 to 10nm and now toward ~3nm, it could be assumed that die size should shrink accordingly. However, with network applications, this assumption has been disproven. For modern FCBGAs, the scale of die and package for networking applications are increasing dramatically. The metal heatsink not only provides thermal emission out of the package but also manages the warpage of a large FCBGA. A large (72 x 72 mm test vehicle) FCBGA is package level reliability (PLR) qualified with a rigid and heavier heat sink. However, when the package is mounted to a PCB, the BGA solder balls melt during reflow since they are not able to uphold the heavier package. This results in low standoff height and solder bridging because the balls flow and connect to adjacent ones. The deviation from Moore’s law and the addition of heatsinks to networking packages, along with other heterogeneously integrated technologies, have a significant impact on system-level warpage. Various package design strategies are discussed in this paper that can be included to control these new sources of warpage.
IMAPS - International Microelectronics Assembly and Packaging Society
Title: Substrate Warpage Study for Heterogeneous Packages
Description:
Warpage formation in semiconductor packages is generally known to occur from coefficient of thermal expansion (CTE) mismatches between multilayered materials with different properties.
The different properties of each printed circuit board (PCB) layer will yield different expansion rates, which will lead to significant high warpage formation under the reflow temperature.
The presence of significant warpage will further induce opened solder joint risks, solder joint collapse for flip chip ball grid arrays (FCBGAs) and so on.
Package warpage is an important factor that impacts board assembly yield, delamination, solder joint fatigue reliability, and other thermal stress issues.
Reducing warpage is a primary concern when trying to enhance the service life of a package.
For years the IC industry has been driven by Moore’s Law assumption that the functionality that fits on a single die will double every 18 to 24 months.
As minimum dimensions have shrunk from 14 to 10nm and now toward ~3nm, it could be assumed that die size should shrink accordingly.
However, with network applications, this assumption has been disproven.
For modern FCBGAs, the scale of die and package for networking applications are increasing dramatically.
The metal heatsink not only provides thermal emission out of the package but also manages the warpage of a large FCBGA.
A large (72 x 72 mm test vehicle) FCBGA is package level reliability (PLR) qualified with a rigid and heavier heat sink.
However, when the package is mounted to a PCB, the BGA solder balls melt during reflow since they are not able to uphold the heavier package.
This results in low standoff height and solder bridging because the balls flow and connect to adjacent ones.
The deviation from Moore’s law and the addition of heatsinks to networking packages, along with other heterogeneously integrated technologies, have a significant impact on system-level warpage.
Various package design strategies are discussed in this paper that can be included to control these new sources of warpage.
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