Hyper BGA Package Assembly: Experimental Design and Process Development

ABSTRACT The increasing complexity of Ball Grid Array (BGA) packages, characterized by larger sizes and finer pitches, necessitates the development of advanced assembly processes to ensure robust yields. This paper addresses the challenges associated with assembling next-generation high performance computing hardware, focusing on lidless ASICs with large BGA packaging, high layer count asymmetrical Printer Circuit Board (PCB) stackups, and the difficulties faced by component package suppliers in controlling warpage. Design of Experiments (DOEs) was conducted to characterize these interactions and develop a reliable assembly process. The study focused specifically on large BGA packages integral to next-generation high performance computing (HPC) hardware platforms. Warpage measurement of BGA was done using the Shadow Moire technique, which simulates reflow temperatures to predict potential SMT process issues. PCB warpage was also characterized using the Shadow Moire technique on high layer count (>36 Layers) hybrid sequential laminated PCBs. The study revealed significant warpage in the packages can impact the SMT (Surface Mount Technology) yields. Experiments were conducted to understand the dynamic warpage characteristics of the PCB and package, gaining further insight into the issues. Process improvements including optimized stencil design, use of copper spacers as well as reflow profile changes, and optimizing SMT fixturing were carried out. The findings from the DOEs were applied to the subsequent build, resulting in a 100% SMT yield. This success was attributed to optimized stencil designs, copper spacers, and reflow temperature adjustments. Key takeaways from the experiments include the importance of close collaboration with Electronic manufacturers, engaging top-tier PCB vendors, and accurately characterizing dynamic warpage behavior. The DOE was instrumental in developing an advanced SMT process for challenging designs, providing a framework for future SMT development and qualification processes.