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Temperature sensitive analytical analysis of gate‐stack dual metal nanowire field‐effect transistor (4H‐SiC)
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AbstractThis article presents an analytical study and effect of temperature (T = 100, 200, 300, 400 K) on various parameters of gate‐stack dual metal nanowire field‐effect transistor (gate‐stack DM NW) FET (4H‐SiC) and gate‐stack dual metal nanowire field‐effect transistor (gate‐stack DM NW FET) (Si). The parabolic approximation is used to solve the 2D Poisson's equation for surface potential, electric field, drain current (Ids), transconductance (gm), output conductance (gd), and analog performance is evaluated. Electron concentration, electron velocity, drain induced barrier lowering, DIBL, and noise figure (NF) have also been investigated for a fair comparison and shows that 4H‐SiC based gate‐stack DM NW FET device is more insensitive to temperature changes than the silicon‐based gate‐stack DM NW FET. Furthermore, gate‐stack DM NW FET (4H‐SiC) has better electrical performance with temperature variation than gate‐stack DM NW FET (Si). The simulations have been carried out using the ATLAS 3D device simulator. Analytical results are in close agreement with the simulated results.
Title: Temperature sensitive analytical analysis of gate‐stack dual metal nanowire field‐effect transistor (4H‐SiC)
Description:
AbstractThis article presents an analytical study and effect of temperature (T = 100, 200, 300, 400 K) on various parameters of gate‐stack dual metal nanowire field‐effect transistor (gate‐stack DM NW) FET (4H‐SiC) and gate‐stack dual metal nanowire field‐effect transistor (gate‐stack DM NW FET) (Si).
The parabolic approximation is used to solve the 2D Poisson's equation for surface potential, electric field, drain current (Ids), transconductance (gm), output conductance (gd), and analog performance is evaluated.
Electron concentration, electron velocity, drain induced barrier lowering, DIBL, and noise figure (NF) have also been investigated for a fair comparison and shows that 4H‐SiC based gate‐stack DM NW FET device is more insensitive to temperature changes than the silicon‐based gate‐stack DM NW FET.
Furthermore, gate‐stack DM NW FET (4H‐SiC) has better electrical performance with temperature variation than gate‐stack DM NW FET (Si).
The simulations have been carried out using the ATLAS 3D device simulator.
Analytical results are in close agreement with the simulated results.
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