Present status and future prospect of VLSI multilevel interconnection

AbstractAs the degree of integration and speed of VLSI are advanced, the multilayered interconnection techniques become increasingly important. At the moment when the VLSI technology is advanced to 0.5 μm technology represented by 16 MDRAMs, electromigration by the high‐current density of Al interconnections and the stress migration by the stress from the interlayer insulating films are important in reliability of Al‐interconnections. Although the latter can be rectified by low‐temperature formation of the insulating films, the prevention of the former is still in a development stage. Since the spacing between the interconnections and the aspect ratio of the connecting hole increase, good planarization of the interlayer insulating films and buried planarization of the connecting holes are required.These problems can be resolved by directive deposition of the insulation films and selective CVD of W. Further, as the miniaturization and the number of interconnection layers are increased, the crosstalk noise of the device due to the interconnection capacitances becomes significant. It is necessary to reduce the film thickness of the insulating layer and the interconnection so that the interconnection capacitance is reduced. In this paper, first the present status of the fine multilevel interconnections, the problems and solutions are presented. Next, the necessity of reduction of the interconnection capacitance and the prospect of the multilevel interconnection in the future after the 0.5 μm generation are described.