Optimized Situational-Aware Multi-Graph Convolutional Recurrent Network Using Pre-Synthesis and Post-Synthesis Power Estimation of VLSI Circuits

Millions of transistors can be integrated onto a single chip using VLSI technology. Early power estimation is crucial in VLSI circuits, as it plays a key role in ensuring their reliability. However, VLSI circuits often suffer from performance drawbacks due to underdeveloped power efficiency evaluation methods, and conventional techniques often suffer from low accuracy and slow processing. Timely and precise power estimation is essential to minimize issues and enhance the reliability of VLSI designs. To overcome these complications, Optimized Situational-aware Multi-graph Convolutional Recurrent Network using Pre-Synthesis and Post-Synthesis Power Estimation of VLSI Circuits (SMCRN-PSPSPE-VLSIC) is proposed. Then input data are collected from ISCAS 89 dataset. The input data are given to the Situational-aware Multi-graph Convolutional Recurrent Network (SMCRN) for Pre-Synthesis and Post-Synthesis Power Estimation (PSPSPE) of the VLSI circuit. Pre-synthesis estimates are generated early in the design process, before the circuit’s physical layout is completed. Post-synthesis estimates, on the other hand, are made after the layout, when more detailed information about the circuit is accessible. The Adam-Dingo Optimization Algorithm (ADOA) is employed to optimize SMCRN parameters that help to enhance the overall power estimation. The performance metrics, like mean absolute error, mean absolute percentage error, root mean square error, mean square error, coefficient of determination are evaluated. The SMCRN-PSPSPE-VLSIC is implemented in Python. The SMCRN-PSPSPE-VLSIC attains 27.69%, 20.38% and 23.54% higher coefficient of determination, 26.36%, 20.69% and 30.29% lower mean absolute error and 12.04%, 13.45% and 22.80% lower root mean square error compared with existing methods, such as PSPSPE-VLSI-RF, IPE-DC-RFNN and PE-VLSI-BART-SAE, respectively.