Open Design of Dual Core Risc-V Multicore Processor

RISC-V set architecture has a significant effect on processor technology due to open instructions that enable researchers to build and enhance computing systems. So, in this paper, an open-source multicore RISC-V processor is implemented. The design is based on an open-source single RvCore processor (Taiga). Two cores of Taiga are integrated considering cache coherence, interconnect, and memory synchronization problems. Therefore, a solution has been developed to achieve data coherence between implemented caches and the main memory; its architecture is mainly based on snoopy protocol. Additionally, a hardware customized peripheral unit has been developed to achieve the synchronization process among working cores. For more consistent and highly controlled memory storage, main memory unit has been designed in dual-port based on AXI protocol in interface, and 4096 lines and word addressable unit. The processor has been implemented in System Verilog HDL. Moreover, extensive testing of the system on various test benches was conducted to assure correct functionality. Hence, the performance of the system has been assessed using standard multicore benchmark (CoreMark). The processor performance has been shown to be comparable to state-of-the-art results.