Turtle Walk: Stopping Timing Attack on NoC

In recent years, several countermeasures such as Gossip NoC, Ironhide, SurfNoC, Adaptive Routing, Random Arbitration, and Guard NoC have been proposed to mitigate micro-architectural timing attacks on Network-on-Chip (NoC) architectures. However, the security of these countermeasures has not been thoroughly validated due to the lack of a standardized testing framework. In this work, we first propose a generalized framework that enables seamless integration of NoC timing-attack countermeasures into the gem5 simulator, upon which representative timing attacks can be launched for systematic evaluation. The throughput values of adversarial packets in the network are then collected as traces and analyzed using Test Vector Leakage Assessment (TVLA) to detect the presence of timing leakage. Our analysis shows that the majority of existing countermeasures such as Adaptive Routing, Gossip NoC, and Random Arbitration are vulnerable to timing attacks as they have high TVLA score. Although countermeasures such as Ironhide and SurfNoC are secure, they restrict their applicability to hybrid topologies and routing algorithms, hence making them impractical for modern NoCs. Moreover, colluding timing attacks are not considered in the design of these countermeasures.To overcome these limitations, we next introduce a novel lightweight countermeasure, Turtle Walk to prevent a multi-PE attack, which leverages existing NoC hardware resources to ensure minimal overhead. It can be deployed on any modern NoCs, addressing the shortcomings of prior defenses. In Turtle Walk, hardware performance counters (HPCs) are used to prevent the attack. Existing HPC-based countermeasures suffer from two major limitations: (1) High false-positive rates due to the absence of a strong correlation between attack behavior and HPC values, and (2) Provide no capability to prevent attacks, even when such attacks are successfully detected. We overcome both limitations by establishing a strong correlation between the necessary conditions of a timing attack on NoC and HPC values, and by triggering the NoC flow-control mechanism based on these values to prevent the attack. Experimental results demonstrate: (1) minimal area overhead of 0.9% for ASIC and 0.3% for FPGA compared to baseline NI hardware without any countermeasure, and (2) no impact on zero-load latency, along with a remarkable ≈ 3x reduction in average packet latency compared to state-of-the-art defenses.