Sidewall spacer optimization for steep switching junctionless transistors

Abstract In this work, we analyze the impact of a high permittivity (high- κ ) sidewall spacer and gate dielectric on the occurrence of sub-60 mV/decade subthreshold swing ( S -swing) in symmetrical junctionless (JL) double gate (DG) transistors. It is shown that steep S -swing values (≤10 mV/decade) can be achieved in JL devices with a combination of a high permittivity (high- κ ) gate dielectric and a narrow low permittivity (low- κ ) sidewall spacer. Implementation of a wider high- κ spacer will diminish the degree of impact ionization by the influence of the fringing component of the gate electric field, and will not be useful for steep off-to-on current transition. A wider spacer with low- κ and a narrow spacer with high- κ permittivity will be useful to limit the latching effect that can occur at lower temperatures (250 K). For high temperature operation, the decrease in the impact ionization rate can be compensated by designing a JL transistor with a thicker silicon film. The work demonstrates opportunities to enhance impact ionization at sub bandgap voltages, and proposes optimal guidelines for selecting a sidewall spacer to facilitate steep switching in JL transistors.