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Bridge Design between AXI Lite and AHB Bus Protocol
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Abstract
Architecture of bridge model between AXI Lite and AHB for this paper were simulated using Synopsys VCS and DC in Verilog HDL. Bridge structure mainly comprises of arbitration techniques, control signals, multiplexing techniques for writing data signals and Decoder for reading data section. In this work, bridge model between AHB and AXI lite was simulated and characterized. The proposed model of bridge design provides efficient communication between on chip bus protocols like AXI and AHB on chip in the era of deep sub-micron technology where channel side is reduced as much as 5 nm.
Title: Bridge Design between AXI Lite and AHB Bus Protocol
Description:
Abstract
Architecture of bridge model between AXI Lite and AHB for this paper were simulated using Synopsys VCS and DC in Verilog HDL.
Bridge structure mainly comprises of arbitration techniques, control signals, multiplexing techniques for writing data signals and Decoder for reading data section.
In this work, bridge model between AHB and AXI lite was simulated and characterized.
The proposed model of bridge design provides efficient communication between on chip bus protocols like AXI and AHB on chip in the era of deep sub-micron technology where channel side is reduced as much as 5 nm.
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