A modified feed-forward linearization of a unique Kapu optimizer CMOS LNA

This study handles the challenges of RF amplifiers at the sub-nanometer scale in 5G systems by developing a high-performance Low Noise Amplifier (LNA) utilizing 45nm CMOS technology. A modified Feed-forward Distortion Cancellation Technique (FFDCT) improves linearity using the Cadence AWR Design Environment, Version 22.1. The design achieves an ultra-low noise figure through three techniques: cascode Inductive Source Degeneration (ISD), optimized by a unique Kapu optimizer, and a modified FFDCT, which enhances the third-order intercept point and minimizes distortion within noise cancellation parameters. A mathematical approach is presented to design the proposed LNA and the modified FFDCT. Thus, the optimized cascode ISD LNA demonstrates favorable tradeoffs among gain, linearity, noise figure, and power consumption. The proposed LNA design demonstrates a nearly flat gain of 27.9dB, an ultra-low noise figure of 0.025dB at 5GHz, and an IIP3 of -14.66 dBm while consuming 1.224 mW of power. As a result of the proposed FFDCT, both NF cancellation and distortion cancellation transpired, which exhibits a minimum noise figure of 0.554dB and an enhanced third-order input intercept (IIP3) of 14.36dB, with a power dissipation of 2.448mW, achieved through the utilization of an auxiliary low-noise amplifier under a 0.6V power supply, which is suitable for wireless applications.