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Multi-Die Embedding in Fan-Out WLP

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ABSTRACT System integration and miniaturization needs, mainly driven by mobile applications, are making advanced semiconductor packaging becoming more diversified and fairly more complex. Development of the so called “More-than-Moore” solutions, the heterogeneous integration of more functionality, distributed on a number of single active and passive elements inside the package, on less footprint and height, is resulting in System-in-Package (SiP) solutions on Package Level and ultimately also on Wafer Level, enabled by Fan-Out Wafer Level Packaging technologies like eWLB (embedded Wafer Level Ball Grid Array). Chip-Package-Board Co-Design and Co-Development are becoming essential keys for time-to-market, first-time-right and last but not least a reasonable cost. While today the majority of SiP is still realized using laminated organic substrate based packages, like BGA and LGA, the need to close the gap to System-on-Chip (SoC) performance, where short connections between the functional areas are inherent, is the challenge of today. Partial disintegration of SoC into two or more dies, requires “SoC like performance” when assembled in SiP. Closer distance of the single functional elements to each other is gaining importance for high performance applications. The application of Wafer Level Packaging (WLP) technology is the consequent next step to address this issue. Reduced form factor and package height can be realized. On top, WLP allows efficient large scale batch processing, resulting in lower cost and higher yield. The limits of Fan-In Wafer Level Packaging (FI-WLP) are addressed by Fan-Out Wafer Level Packaging (FO-WLP), which is the enabler for System-in-Package on Wafer Level (WLSiP). We are on the way from Single Die FO-WLP to Multi-Die FO-WLP and WLSiP. The paper presents an up-to-date overview about the status of the work done at NANIUM related to FO-WLP as enabler for WLSiP. It will focus on the latest advances of multi-die embedding side-by-side (SbS), and it will also show the status of technology brick and tool box development for 3D integration using eWLB as active interposer in different PoP (Package-on-Package) variants.
Title: Multi-Die Embedding in Fan-Out WLP
Description:
ABSTRACT System integration and miniaturization needs, mainly driven by mobile applications, are making advanced semiconductor packaging becoming more diversified and fairly more complex.
Development of the so called “More-than-Moore” solutions, the heterogeneous integration of more functionality, distributed on a number of single active and passive elements inside the package, on less footprint and height, is resulting in System-in-Package (SiP) solutions on Package Level and ultimately also on Wafer Level, enabled by Fan-Out Wafer Level Packaging technologies like eWLB (embedded Wafer Level Ball Grid Array).
Chip-Package-Board Co-Design and Co-Development are becoming essential keys for time-to-market, first-time-right and last but not least a reasonable cost.
While today the majority of SiP is still realized using laminated organic substrate based packages, like BGA and LGA, the need to close the gap to System-on-Chip (SoC) performance, where short connections between the functional areas are inherent, is the challenge of today.
Partial disintegration of SoC into two or more dies, requires “SoC like performance” when assembled in SiP.
Closer distance of the single functional elements to each other is gaining importance for high performance applications.
The application of Wafer Level Packaging (WLP) technology is the consequent next step to address this issue.
Reduced form factor and package height can be realized.
On top, WLP allows efficient large scale batch processing, resulting in lower cost and higher yield.
The limits of Fan-In Wafer Level Packaging (FI-WLP) are addressed by Fan-Out Wafer Level Packaging (FO-WLP), which is the enabler for System-in-Package on Wafer Level (WLSiP).
We are on the way from Single Die FO-WLP to Multi-Die FO-WLP and WLSiP.
The paper presents an up-to-date overview about the status of the work done at NANIUM related to FO-WLP as enabler for WLSiP.
It will focus on the latest advances of multi-die embedding side-by-side (SbS), and it will also show the status of technology brick and tool box development for 3D integration using eWLB as active interposer in different PoP (Package-on-Package) variants.

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