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Metrology and Inspection for New Interconnects in Advanced Packaging
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Interconnects for Advanced Packaging are getting smaller and come in a variety of sizes, shapes, and materials. The height, diameter, shape, and the absence/presence of these interconnects are critical and must be monitored across the device and wafer to ensure reliable connections during the bonding process.
Solder bump technologies have been utilized in the past, but cannot support the high density interconnects that are required. New interconnect technologies being utilized for wafer level packaging (WLP) and through silicon via (TSV) packages include copper pillar posts and TSV posts. These new interconnect technologies provide higher density, improved reliability, and better electrical performance.
This paper will highlight the critical metrology and inspection requirements for these new interconnect technologies and demonstrate the capability of a single platform to support these new interconnects for high volume manufacturing (HVM).
The single platform includes 3D metrology performed using a proprietary interferometric sensor technology that can measure the height of the post and the thickness of the surrounding polymer at the same time to optimize the measurement performance and system throughput. The platform also provides the ability to inspect for surface defects, irregular posts, missing posts, and a variety of other inspections typically performed on bumped wafers or substrates.
Both the metrology and inspection results from the single platform are output to a proprietary analysis package using industry standard Rudolph Result Files (RRF). The analysis will demonstrate the value these results provide for process control and the defect analysis, ultimately leading to improved yields and equipment utilization.
IMAPS - International Microelectronics Assembly and Packaging Society
Title: Metrology and Inspection for New Interconnects in Advanced Packaging
Description:
Interconnects for Advanced Packaging are getting smaller and come in a variety of sizes, shapes, and materials.
The height, diameter, shape, and the absence/presence of these interconnects are critical and must be monitored across the device and wafer to ensure reliable connections during the bonding process.
Solder bump technologies have been utilized in the past, but cannot support the high density interconnects that are required.
New interconnect technologies being utilized for wafer level packaging (WLP) and through silicon via (TSV) packages include copper pillar posts and TSV posts.
These new interconnect technologies provide higher density, improved reliability, and better electrical performance.
This paper will highlight the critical metrology and inspection requirements for these new interconnect technologies and demonstrate the capability of a single platform to support these new interconnects for high volume manufacturing (HVM).
The single platform includes 3D metrology performed using a proprietary interferometric sensor technology that can measure the height of the post and the thickness of the surrounding polymer at the same time to optimize the measurement performance and system throughput.
The platform also provides the ability to inspect for surface defects, irregular posts, missing posts, and a variety of other inspections typically performed on bumped wafers or substrates.
Both the metrology and inspection results from the single platform are output to a proprietary analysis package using industry standard Rudolph Result Files (RRF).
The analysis will demonstrate the value these results provide for process control and the defect analysis, ultimately leading to improved yields and equipment utilization.
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