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Development of Low-power Coherent ASIC
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The latest generation of coherent pluggable modules impose strict power limits on the coherent ASIC. The development process for a low-power coherent ASIC designed in a 7nm FINFET process is described. The ASIC enables pluggable coherent modules with energy efficiency of 40-60pJ/bit for various 400G DWDM applications.
Title: Development of Low-power Coherent ASIC
Description:
The latest generation of coherent pluggable modules impose strict power limits on the coherent ASIC.
The development process for a low-power coherent ASIC designed in a 7nm FINFET process is described.
The ASIC enables pluggable coherent modules with energy efficiency of 40-60pJ/bit for various 400G DWDM applications.
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